United States
PwrQ Holdings LLC
Apple
CPU Performance Engineer, Platform Architecture
United States
Cupertino, California, United States · Cambridge, Massachusetts, United States · Beaverton, Oregon, United States · Austin, Texas, United States
PythonC++
About the opportunity
The CPU Platform Architecture team is responsible for pushing the boundaries of both single-threaded and multi-threaded CPU performance, to enhance the user experience of many Apple products. The team is composed of experts with deep experience in microarchitecture, ISA definition, performance modeling, power modeling, and workload analysis. We are seeking a highly motivated, innovative, and confident individual to join the CPU Platform Architecture team to help drive advanced exploration for next-generation iPhone, iPad, Mac, and server CPU designs.
DESCRIPTION
As a CPU Performance Engineer with a focus on the memory subsystem, you will be part of a team that is defining and optimizing CPU and cache micro-architecture. Working collaboratively, you will seek out areas of the design for improvement by identifying performance bottlenecks and evaluate ideas to address them. You will engage with experienced CPU and SoC designers in micro-architecture and RTL to assess the feasibility of ideas through modeling, refine ideas and model correlation, and seed new ideas. The role requires the analysis of single-threaded and multi-threaded workloads across existing and new product categories to identify bottlenecks and opportunities for improvement. We collaborate as a larger CPU architecture and performance team to maintain and improve the simulation environment to enable data- driven decisions and always look for ways to boost the productivity of the entire team.
MINIMUM QUALIFICATIONS
- BS degree
- Experience in CPU and SOC architecture and micro-architecture
- Experience with performance simulation environments
- Object-oriented programming experience in C/C++
- Experience in a scripting language such as Perl or Python
PREFERRED QUALIFICATIONS
- Knowledge of memory latency tolerance techniques or other aspects of CPU memory subsystem (i.e. prefetching, caching policies)
- 3+ years of relevant industry experience
- MS or PhD in Electrical or Computer Engineering or Computer Science
- Understanding of common data structures and algorithms
- Familiarity with SIMD, vector, or accelerator architectures
- Familiarity with MP performance
- Comfortable in an environment of uncertainty and able to navigate through ambiguities
- Experience in a research-driven environment
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